Generating schematic for design: PARITY
The schematic for design 'PARITY' has 1 page(s).

1
design_analyzer> report_timing
Information: Updating design information... (UID-85)
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : PARITY
Version: 1999.05
Date   : Tue Sep 14 13:04:58 1999
****************************************

Operating Conditions: 
Wire Load Model Mode: top

  Startpoint: A[19] (input port)
  Endpoint: Y (output port)
  Path Group: (none)
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  PARITY             05x05                 class

  Point                                    Incr       Path
  -----------------------------------------------------------
  input external delay                     0.00       0.00 f
  A[19] (in)                               0.00       0.00 f
  U27/Z (EO)                               1.22       1.22 f
  U28/Z (EO)                               1.22       2.43 f
  U36/Z (EO)                               1.22       3.65 f
  U43/Z (EO)                               1.22       4.86 f
  U55/Z (EO)                               1.22       6.08 f
  U13/Z (EO)                               1.09       7.17 f
  Y (out)                                  0.00       7.17 f
  data arrival time                                   7.17
  -----------------------------------------------------------
  (Path is unconstrained)