# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 12.3 Build EDK_MS3.70d
# Wed Jan 19 13:19:03 2011
# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
# Family:    virtex4
# Device:    xc4vfx12
# Package:   ff668
# Speed Grade:  -10
# Processor number: 1
# Processor 1: ppc405_0
# Processor clock frequency: 100.0
# Bus clock frequency: 50.0
# Debug Interface: FPGA JTAG
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT lm_bit_clk = lm_bit_clk, DIR = I, SIGIS = CLK
 PORT lm_sdata_in = lm_sdata_in, DIR = I
 PORT lm_sdata_out = lm_sdata_out, DIR = O
 PORT lm_sync = lm_sync, DIR = O
 PORT lm_reset_n = lm_reset_n, DIR = O
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO_pin, DIR = IO, VEC = [0:3]
 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
 PORT fpga_0_Push_Buttons_Position_GPIO_IO_pin = fpga_0_Push_Buttons_Position_GPIO_IO_pin, DIR = IO, VEC = [0:4]
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0


BEGIN ppc405_virtex4
 PARAMETER INSTANCE = ppc405_0
 PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
 PARAMETER C_IDCR_BASEADDR = 0b0100000000
 PARAMETER C_IDCR_HIGHADDR = 0b0111111111
 PARAMETER HW_VER = 2.01.b
 BUS_INTERFACE DPLB0 = plb
 BUS_INTERFACE IPLB0 = plb
 BUS_INTERFACE JTAGPPC = ppc405_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC405CLOCK = clk_100_0000MHzDCM0
 PORT EICC405EXTINPUTIRQ = ppc405_0_EICC405EXTINPUTIRQ
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_50_0000MHzDCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00000fff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
# # USER CONNECT BEGIN ##
 PORT BRAM_Rst_B = xps_bram_if_cntlr_1_port_BRAM_Rst
 PORT BRAM_Clk_B = xps_bram_if_cntlr_1_port_BRAM_Clk
 PORT BRAM_EN_B = im_rx_en
 PORT BRAM_WEN_B = im_rx_wen
 PORT BRAM_Addr_B = im_rx_addr
 PORT BRAM_Dout_B = im_rx_data
END

# # USER CONNECT END ##
BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_GPIO_WIDTH = 4
# PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81440000
 PARAMETER C_HIGHADDR = 0x8144ffff
 BUS_INTERFACE SPLB = plb
# PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO_pin
END

BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_Positions
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = plb
 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
END

BEGIN xps_gpio
 PARAMETER INSTANCE = Push_Buttons_Position
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_GPIO_WIDTH = 5
# PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = plb
# PORT IP2INTC_Irpt = Push_Buttons_Position_IP2INTC_Irpt
 PORT GPIO_IO = fpga_0_Push_Buttons_Position_GPIO_IO_pin
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_0
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xffff0000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_port
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_2
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00001000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_2_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_0_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_2_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_2_port
# # USER CONNECT BEGIN ##
 PORT BRAM_Rst_B = xps_bram_if_cntlr_2_port_BRAM_Rst
 PORT BRAM_Clk_B = xps_bram_if_cntlr_2_port_BRAM_Clk
 PORT BRAM_EN_B = im_tx_en
 PORT BRAM_WEN_B = im_tx_wen
 PORT BRAM_Addr_B = im_tx_addr
 PORT BRAM_Din_B = im_tx_data
END

# # USER CONNECT END ##
BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = DCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 50000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 4.00.a
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_100_0000MHzDCM0
 PORT CLKOUT1 = clk_50_0000MHzDCM0
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_inst
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = ppc405_0_jtagppc_bus
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 3.00.a
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = clk_50_0000MHzDCM0
 PORT Ext_Reset_In = sys_rst_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = plb
 PORT Intr = rx_intr
 PORT Irq = ppc405_0_EICC405EXTINPUTIRQ
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_USE_UART = 1
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = plb
END

BEGIN plb_codec_cntlr
 PARAMETER INSTANCE = plb_codec_cntlr_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81460000
 PARAMETER C_HIGHADDR = 0x81460fff
 BUS_INTERFACE SPLB = plb
 PORT lm_bit_clk = lm_bit_clk
 PORT reset_n = sys_rst_s
 PORT lm_sdata_in = lm_sdata_in
 PORT lm_sdata_out = lm_sdata_out
 PORT lm_sync = lm_sync
 PORT lm_reset_n = lm_reset_n
 PORT im_rx_en = im_rx_en
 PORT im_rx_wen = im_rx_wen
 PORT im_rx_addr = im_rx_addr
 PORT im_rx_data = im_rx_data
 PORT rx_intr = rx_intr
 PORT im_tx_data = im_tx_data
 PORT im_tx_en = im_tx_en
 PORT im_tx_wen = im_tx_wen
 PORT im_tx_addr = im_tx_addr
END