-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:26:11 10/05/2011 -- Design Name: -- Module Name: C:/Xilinx/work/new1/test_counter.vhd -- Project Name: new1 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: counter -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_counter IS END test_counter; ARCHITECTURE behavior OF test_counter IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT counter PORT( sysclk : IN std_logic; reset : IN std_logic; output : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal sysclk : std_logic := '0'; signal reset : std_logic := '0'; --Outputs signal output : std_logic_vector(3 downto 0); -- Clock period definitions constant sysclk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: counter PORT MAP ( sysclk => sysclk, reset => reset, output => output ); -- Clock process definitions sysclk_process :process begin sysclk <= '0'; wait for sysclk_period/2; sysclk <= '1'; wait for sysclk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for sysclk_period*10; -- insert stimulus here reset <= '1'; wait; end process; END;